gr-baz Package
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#include "rtl2832.h"
Go to the source code of this file.
Classes | |
struct | e4k_pll_params |
struct | e4k_state |
struct | reg_field |
struct | reg_field_ops |
class | RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k |
Namespaces | |
namespace | RTL2832_NAMESPACE |
namespace | RTL2832_NAMESPACE::TUNERS_NAMESPACE |
Functions | |
uint32_t | reg_field_read (struct reg_field_ops *ops, struct reg_field *field) |
int | reg_field_write (struct reg_field_ops *ops, struct reg_field *field, uint32_t val) |
int | reg_field_cmd (struct cmd_state *cs, enum cmd_op op, const char *cmd, int argc, char **argv, struct reg_field_ops *ops) |
int | e4k_init (struct e4k_state *e4k, bool enable_dc_offset_loop=true, bool set_manual_gain=false) |
int | e4k_if_gain_set (struct e4k_state *e4k, uint8_t stage, int8_t value) |
int | e4k_mixer_gain_set (struct e4k_state *e4k, int8_t value) |
int | e4k_commonmode_set (struct e4k_state *e4k, int8_t value) |
int | e4k_tune_freq (struct e4k_state *e4k, uint32_t freq) |
int | e4k_tune_params (struct e4k_state *e4k, struct e4k_pll_params *p) |
int | e4k_compute_pll_params (struct e4k_pll_params *oscp, uint32_t fosc, uint32_t intended_flo) |
int | e4k_if_filter_bw_get (struct e4k_state *e4k, enum e4k_if_filter filter) |
int | e4k_if_filter_bw_set (struct e4k_state *e4k, enum e4k_if_filter filter, uint32_t bandwidth) |
int | e4k_if_filter_chan_enable (struct e4k_state *e4k, int on) |
int | e4k_rf_filter_set (struct e4k_state *e4k) |
int | sam3u_e4k_init (struct e4k_state *e4k, void *i2c, uint8_t slave_addr) |
void | sam3u_e4k_power (struct e4k_state *e4k, int on) |
void | sam3u_e4k_stby (struct e4k_state *e4k, int on) |
int | e4k_manual_dc_offset (struct e4k_state *e4k, int8_t iofs, int8_t irange, int8_t qofs, int8_t qrange) |
int | e4k_dc_offset_calibrate (struct e4k_state *e4k) |
int | e4k_dc_offset_gen_table (struct e4k_state *e4k) |
#define E4K_AGC11_LNA_GAIN_ENH (1 << 0) |
#define E4K_AGC1_LIN_MODE (1 << 4) |
#define E4K_AGC1_LNA_G_HIGH (1 << 7) |
#define E4K_AGC1_LNA_G_LOW (1 << 6) |
#define E4K_AGC1_LNA_UPDATE (1 << 5) |
#define E4K_AGC1_MOD_MASK 0xF |
#define E4K_AGC6_LNA_CAL_REQ (1 << 4) |
#define E4K_AGC7_GAIN_STEP_5dB (1 << 5) |
#define E4K_AGC7_MIX_GAIN_AUTO (1 << 0) |
#define E4K_AGC8_SENS_LIN_AUTO (1 << 0) |
#define E4K_CHFCALIB_CMD (1 << 0) |
#define E4K_CLKOUT_DISABLE 0x96 |
#define E4K_DC1_CAL_REQ (1 << 0) |
#define E4K_DC5_I_LUT_EN (1 << 0) |
#define E4K_DC5_Q_LUT_EN (1 << 1) |
#define E4K_DC5_RANGE_DET_EN (1 << 2) |
#define E4K_DC5_RANGE_EN (1 << 3) |
#define E4K_DC5_TIMEVAR_EN (1 << 4) |
#define E4K_FILT3_DISABLE (1 << 5) |
#define E4K_MASTER1_NORM_STBY (1 << 1) |
#define E4K_MASTER1_POR_DET (1 << 2) |
#define E4K_MASTER1_RESET (1 << 0) |
#define E4K_SYNTH1_BAND_SHIF 1 |
#define E4K_SYNTH1_PLL_LOCK (1 << 0) |
#define E4K_SYNTH7_3PHASE_EN (1 << 3) |
#define E4K_SYNTH8_VCOCAL_UPD (1 << 2) |
#define RTL2832_E4000_ADDITIONAL_INIT_REG_TABLE_LEN 34 |
#define RTL2832_E4000_IF_STAGE_1_GAIN_ADDR 0x16 |
#define RTL2832_E4000_IF_STAGE_1_GAIN_MASK 0x1 |
#define RTL2832_E4000_IF_STAGE_1_GAIN_SHIFT 0 |
#define RTL2832_E4000_IF_STAGE_1_GAIN_TABLE_LEN 2 |
#define RTL2832_E4000_IF_STAGE_2_GAIN_ADDR 0x16 |
#define RTL2832_E4000_IF_STAGE_2_GAIN_MASK 0x6 |
#define RTL2832_E4000_IF_STAGE_2_GAIN_SHIFT 1 |
#define RTL2832_E4000_IF_STAGE_2_GAIN_TABLE_LEN 4 |
#define RTL2832_E4000_IF_STAGE_3_GAIN_ADDR 0x16 |
#define RTL2832_E4000_IF_STAGE_3_GAIN_MASK 0x18 |
#define RTL2832_E4000_IF_STAGE_3_GAIN_SHIFT 3 |
#define RTL2832_E4000_IF_STAGE_3_GAIN_TABLE_LEN 4 |
#define RTL2832_E4000_IF_STAGE_4_GAIN_ADDR 0x16 |
#define RTL2832_E4000_IF_STAGE_4_GAIN_MASK 0x60 |
#define RTL2832_E4000_IF_STAGE_4_GAIN_SHIFT 5 |
#define RTL2832_E4000_IF_STAGE_4_GAIN_TABLE_LEN 4 |
#define RTL2832_E4000_IF_STAGE_5_GAIN_ADDR 0x17 |
#define RTL2832_E4000_IF_STAGE_5_GAIN_MASK 0x7 |
#define RTL2832_E4000_IF_STAGE_5_GAIN_SHIFT 0 |
#define RTL2832_E4000_IF_STAGE_5_GAIN_TABLE_LEN 8 |
#define RTL2832_E4000_IF_STAGE_6_GAIN_ADDR 0x17 |
#define RTL2832_E4000_IF_STAGE_6_GAIN_MASK 0x38 |
#define RTL2832_E4000_IF_STAGE_6_GAIN_SHIFT 3 |
#define RTL2832_E4000_IF_STAGE_6_GAIN_TABLE_LEN 8 |
#define RTL2832_E4000_LNA_GAIN_ADD_ADDR 0x24 |
#define RTL2832_E4000_LNA_GAIN_ADD_MASK 0x7 |
#define RTL2832_E4000_LNA_GAIN_ADD_SHIFT 0 |
#define RTL2832_E4000_LNA_GAIN_ADD_TABLE_LEN 8 |
#define RTL2832_E4000_LNA_GAIN_ADDR 0x14 |
#define RTL2832_E4000_LNA_GAIN_BAND_NUM 2 |
#define RTL2832_E4000_LNA_GAIN_MASK 0xf |
#define RTL2832_E4000_LNA_GAIN_SHIFT 0 |
#define RTL2832_E4000_LNA_GAIN_TABLE_LEN 16 |
#define RTL2832_E4000_MIXER_GAIN_ADDR 0x15 |
#define RTL2832_E4000_MIXER_GAIN_BAND_NUM 2 |
#define RTL2832_E4000_MIXER_GAIN_MASK 0x1 |
#define RTL2832_E4000_MIXER_GAIN_SHIFT 0 |
#define RTL2832_E4000_MIXER_GAIN_TABLE_LEN 2 |
#define RTL2832_E4000_RF_BAND_BOUNDARY_HZ 300000000 |
#define RTL2832_E4000_TUNER_MODE_UPDATE_WAIT_TIME_MS 1000 |
#define RTL2832_E4000_TUNER_OUTPUT_POWER_UNIT_0P1_DBM -100 |
enum cmd_op |
enum e4k_agc_mode |
enum e4k_band |
enum e4k_if_filter |
enum e4k_mixer_filter_bw |
enum e4k_reg |
int e4k_commonmode_set | ( | struct e4k_state * | e4k, |
int8_t | value | ||
) |
int e4k_compute_pll_params | ( | struct e4k_pll_params * | oscp, |
uint32_t | fosc, | ||
uint32_t | intended_flo | ||
) |
int e4k_dc_offset_calibrate | ( | struct e4k_state * | e4k | ) |
int e4k_dc_offset_gen_table | ( | struct e4k_state * | e4k | ) |
int e4k_if_filter_bw_get | ( | struct e4k_state * | e4k, |
enum e4k_if_filter | filter | ||
) |
int e4k_if_filter_bw_set | ( | struct e4k_state * | e4k, |
enum e4k_if_filter | filter, | ||
uint32_t | bandwidth | ||
) |
int e4k_if_filter_chan_enable | ( | struct e4k_state * | e4k, |
int | on | ||
) |
int e4k_if_gain_set | ( | struct e4k_state * | e4k, |
uint8_t | stage, | ||
int8_t | value | ||
) |
int e4k_init | ( | struct e4k_state * | e4k, |
bool | enable_dc_offset_loop = true , |
||
bool | set_manual_gain = false |
||
) |
int e4k_manual_dc_offset | ( | struct e4k_state * | e4k, |
int8_t | iofs, | ||
int8_t | irange, | ||
int8_t | qofs, | ||
int8_t | qrange | ||
) |
int e4k_mixer_gain_set | ( | struct e4k_state * | e4k, |
int8_t | value | ||
) |
int e4k_rf_filter_set | ( | struct e4k_state * | e4k | ) |
int e4k_tune_freq | ( | struct e4k_state * | e4k, |
uint32_t | freq | ||
) |
int e4k_tune_params | ( | struct e4k_state * | e4k, |
struct e4k_pll_params * | p | ||
) |
int reg_field_cmd | ( | struct cmd_state * | cs, |
enum cmd_op | op, | ||
const char * | cmd, | ||
int | argc, | ||
char ** | argv, | ||
struct reg_field_ops * | ops | ||
) |
uint32_t reg_field_read | ( | struct reg_field_ops * | ops, |
struct reg_field * | field | ||
) |
int reg_field_write | ( | struct reg_field_ops * | ops, |
struct reg_field * | field, | ||
uint32_t | val | ||
) |
int sam3u_e4k_init | ( | struct e4k_state * | e4k, |
void * | i2c, | ||
uint8_t | slave_addr | ||
) |
void sam3u_e4k_power | ( | struct e4k_state * | e4k, |
int | on | ||
) |
void sam3u_e4k_stby | ( | struct e4k_state * | e4k, |
int | on | ||
) |